M.S. Completed
2014.Oct.22After disappearing for the better part of a year to complete my thesis and get a first author paper submitted, I finally got notice of my completion. The last two years have finally been realized! Woohoo! Now, I just hope my ASPLOS submission gets accepted. If it does (reviews are good), I may even get to present it in Istanbul, Turkey, in March.
Spartan Tetris
2014.Jan.30Latest class project: Tetris (report, in action). This was a good challenge. I used a Spartan 3E Starter Kit to develop it. The built in click knob was used to control the pieces, a custom VGA core was built to control the display, and the software was completely from scratch. The software used an event queue with an atomic (non-interruptable) event handler to process events, but used interrupts to populate the event queue. The design was based on QP-Nano, but is not nearly as fully featured; initially, I was going to use that framework, but the memory requirements were too large, resulting in complete design from scratch. There were some issues that could be resolved (click knob is software debounced and should be handled in hardware, some graphical glitches with end game scenarios), but this was more of a fun project than one that needs to be finished.
CSI: Super-Scalar Dispatch Unit
2013.Apr.14I finished the super-scalar dispatch unit with exception handling for ECE 254A ahead of schedule. Overall, it's a pretty good system, but definitely not production grade. As a starting point, it can be developed into something bigger and more stable than it's current state. There are some definite bugs and it could use some regression testing to flush out what I'm sure are several dozen bugs. There are a couple known issues: the completion file for exception handling is only 32-entries deep and does not wrap; instruction 0 in the completion file must not cause a page fault.
Thoughts on Project Planning
2013.Feb.15The last 3 weeks were spent developing a memory hierarchy for ECE 254A, Advanced Computer Architecture. I managed to design, test, and document a multi-core coherent L1/L2 cache and memory hierarchy in that time. The main takeaway from the project was not the design or amount of work that went into it, but a decision to rework my design efforts for future projects like this.
I was in a time crunch by the end of the project because I approached the work the way that I did when I was at PMC. Taking the design requirements (about a 1 sentence description, with any additional questions answered in class) I started by documenting the key features and figuring out how to implement them in a complete way. However, I wound up focusing on making something complete and that worked. Period. Complicated projects that have a 3 week cycle are not going to be fully complete.
For the next projects, I realized that the design is not the point, but the report and passing testcases are. For this next project, a super-scalar dispatch unit, I'm going to start with my testcases defined and ranked in importance. Then the focus becomes getting the tests passing, followed by getting the report written. The report will get 2-3 days to be written as completely as possible. The design is finished once all the tests are passing or there are only 2-3 days left write the report.
Welcome to Hectic Tech!
2013.Jan.18We have just opened our doors. The dust is flying almost as fast as the code at this point. HT provides engineering design and support for VLSI, FPGA and embedded projects that lack expertise, resources, or time. Please email for more information.
