1 /******************************************************************************
  2 * Copyright 2013, Hectic Tech (Jeff Heckey). All rights reserved
  3 ******************************************************************************/
  4 
  5 module tb_dispatch;
  6 
  7 parameter PC = 8;
  8 parameter OP = 3;
  9 parameter TAG = 4;
 10 parameter ADDR = 32;
 11 parameter DATA = 32;
 12 
 13 localparam STOR = 3'b111,
 14            LOAD = 3'b110,
 15            FDIV = 3'b101,
 16            FMUL = 3'b100,
 17            FSUB = 3'b011,
 18            FADD = 3'b010;
 19 
 20 localparam R0 = 4'd4,
 21            R1 = 4'd5,
 22            R2 = 4'd6,
 23            R3 = 4'd7,
 24            A0 = 4'd8,
 25            A1 = 4'd9,
 26            M0 = 4'd10,
 27            M1 = 4'd11,
 28            L0 = 4'd12,
 29            L1 = 4'd13,
 30            S0 = 4'd14,
 31            S1 = 4'd15;
 32 
 33 reg                     clk;
 34 reg                     rstn;
 35 reg  [PC-1:0]           rptr;
 36 
 37 wire [7:0]              regstat_busy;
 38 wire [4*TAG-1:0]        regstat_remap;
 39 
 40 reg  [OP+3*TAG+ADDR-1:0] instq[63:0];
 41 wire [OP+3*TAG+ADDR-1:0] inst0 = (rstn && instq[rptr]      !== {OP+3*TAG+ADDR{1'bX}}) ? instq[rptr]      : {OP+3*TAG+ADDR{1'b0}};
 42 wire [OP+3*TAG+ADDR-1:0] inst1 = (rstn && instq[rptr+8'd1] !== {OP+3*TAG+ADDR{1'bX}}) ? instq[rptr+8'd1] : {OP+3*TAG+ADDR{1'b0}};
 43 
 44 wire [OP+4*TAG+ADDR-1:0]    disp_bus0;
 45 wire [OP+4*TAG+ADDR-1:0]    disp_bus1;
 46 
 47 // Unpack for debugging
 48 wire [OP-1:0]               disp0_op    = disp_bus0[OP+3*TAG+ADDR-1:3*TAG+ADDR];
 49 wire [TAG-1:0]              disp0_rsv   = disp_bus0[OP+4*TAG+ADDR-1:OP+3*TAG+ADDR];
 50 wire [TAG-1:0]              disp0_dst   = disp_bus0[3*TAG+ADDR-1:2*TAG+ADDR];
 51 wire [TAG-1:0]              disp0_src1  = disp_bus0[2*TAG+ADDR-1:TAG+ADDR];
 52 wire [TAG-1:0]              disp0_src2  = disp_bus0[TAG+ADDR-1:ADDR];
 53 wire [OP-1:0]               disp1_op    = disp_bus1[OP+3*TAG+ADDR-1:3*TAG+ADDR];
 54 wire [TAG-1:0]              disp1_rsv   = disp_bus1[OP+4*TAG+ADDR-1:OP+3*TAG+ADDR];
 55 wire [TAG-1:0]              disp1_dst   = disp_bus1[3*TAG+ADDR-1:2*TAG+ADDR];
 56 wire [TAG-1:0]              disp1_src1  = disp_bus1[2*TAG+ADDR-1:TAG+ADDR];
 57 wire [TAG-1:0]              disp1_src2  = disp_bus1[TAG+ADDR-1:ADDR];
 58 
 59 wire                    exception;
 60 wire [PC-1:0]           comp_pc;
 61 wire                    clean;
 62 wire                    cf_val;
 63 wire [TAG-1:0]          cf_addr;
 64 wire [DATA-1:0]         cf_data;
 65 
 66 wire [TAG-1:0]          cdb_r0_id;
 67 wire [DATA-1:0]         cdb_r0_data;
 68 wire [TAG-1:0]          cdb_r1_id;
 69 wire [DATA-1:0]         cdb_r1_data;
 70 wire [TAG-1:0]          cdb_r2_id;
 71 wire [DATA-1:0]         cdb_r2_data;
 72 reg                     cdb_a_except;
 73 reg  [TAG-1:0]          cdb_a_id;
 74 reg  [DATA-1:0]         cdb_a_data;
 75 reg                     cdb_m_except;
 76 reg  [TAG-1:0]          cdb_m_id;
 77 reg  [DATA-1:0]         cdb_m_data;
 78 reg                     cdb_l_except;
 79 reg  [TAG-1:0]          cdb_l_id;
 80 reg  [DATA-1:0]         cdb_l_data;
 81 reg                     cdb_s_except;
 82 reg  [TAG-1:0]          cdb_s_id;
 83 reg  [DATA-1:0]         cdb_s_data;
 84 
 85 wire [1:0]              fadd_val;
 86 reg  [1:0]              fadd_ack;
 87 reg  [TAG+DATA+1:0]       fadd_pipe[2:0];
 88 wire [OP-1:0]           fadd0_op;
 89 wire [DATA-1:0]         fadd0_src1;
 90 wire [DATA-1:0]         fadd0_src2;
 91 wire [OP-1:0]           fadd1_op;
 92 wire [DATA-1:0]         fadd1_src1;
 93 wire [DATA-1:0]         fadd1_src2;
 94 
 95 wire [1:0]              fmul_val;
 96 reg  [1:0]              fmul_ack;
 97 reg  [TAG+DATA+1:0]       fmul_pipe[4:0];
 98 wire [OP-1:0]           fmul0_op;
 99 wire [DATA-1:0]         fmul0_src1;
100 wire [DATA-1:0]         fmul0_src2;
101 wire [OP-1:0]           fmul1_op;
102 wire [DATA-1:0]         fmul1_src1;
103 wire [DATA-1:0]         fmul1_src2;
104 
105 wire [1:0]              load_val;
106 reg  [1:0]              load_ack;
107 reg  [TAG+DATA:0]       load_pipe;
108 wire [ADDR-1:0]         load0_address;
109 wire [OP-1:0]           load0_op;
110 wire [TAG-1:0]          load0_stall;
111 wire [ADDR-1:0]         load1_address;
112 wire [OP-1:0]           load1_op;
113 wire [TAG-1:0]          load1_stall;
114 
115 wire [1:0]              store_val;
116 wire [1:0]              store_ack;
117 reg  [TAG+DATA:0]       store_pipe;
118 wire [ADDR-1:0]         store0_address;
119 wire [DATA-1:0]         store0_data;
120 wire [OP-1:0]           store0_op;
121 wire [PC-1:0]           store0_pc;
122 wire [TAG-1:0]          store0_stall;
123 wire [ADDR-1:0]         store1_address;
124 wire [DATA-1:0]         store1_data;
125 wire [OP-1:0]           store1_op;
126 wire [PC-1:0]           store1_pc;
127 wire [TAG-1:0]          store1_stall;
128 
129 /*AUTOWIRE*/
130 // Beginning of automatic wires (for undeclared instantiated-module outputs)
131 wire [1:0]              inst_pop;               // From dispatch of dispatch.v
132 // End of automatics
133 /*AUTOREG*/
134 
135 
136 dispatch dispatch (
137     /*AUTOINST*/
138                    // Outputs
139                    .inst_pop            (inst_pop[1:0]),
140                    .disp_bus0           (disp_bus0[OP+4*TAG+ADDR-1:0]),
141                    .disp_bus1           (disp_bus1[OP+4*TAG+ADDR-1:0]),
142                    // Inputs
143                    .clk                 (clk),
144                    .rstn                (rstn),
145                    .inst0               (inst0[OP+3*TAG+ADDR-1:0]),
146                    .inst1               (inst1[OP+3*TAG+ADDR-1:0]),
147                    .cdb_a_id            (cdb_a_id[TAG-1:0]),
148                    .cdb_a_except        (cdb_a_except),
149                    .cdb_m_id            (cdb_m_id[TAG-1:0]),
150                    .cdb_m_except        (cdb_m_except),
151                    .cdb_l_id            (cdb_l_id[TAG-1:0]),
152                    .cdb_l_except        (cdb_l_except),
153                    .cdb_s_id            (cdb_s_id[TAG-1:0]),
154                    .cdb_s_except        (cdb_s_except),
155                    .regstat_busy        (regstat_busy[7:0]),
156                    .regstat_remap       (regstat_remap[4*TAG-1:0]));
157 
158 regstat regstat (
159     /*AUTOINST*/
160                  // Outputs
161                  .regstat_busy          (regstat_busy[7:0]),
162                  .regstat_remap         (regstat_remap[4*TAG-1:0]),
163                  // Inputs
164                  .clk                   (clk),
165                  .rstn                  (rstn),
166                  .disp0_dst             (disp_bus0[3*TAG+ADDR-1:2*TAG+ADDR]),
167                  .disp0_rsv             (disp_bus0[OP+4*TAG+ADDR-1:OP+3*TAG+ADDR]),
168                  .disp1_dst             (disp_bus1[3*TAG+ADDR-1:2*TAG+ADDR]),
169                  .disp1_rsv             (disp_bus1[OP+4*TAG+ADDR-1:OP+3*TAG+ADDR]),
170                  .cdb_a_id              (cdb_a_id[TAG-1:0]),
171                  .cdb_m_id              (cdb_m_id[TAG-1:0]),
172                  .cdb_l_id              (cdb_l_id[TAG-1:0]),
173                  .cdb_s_id              (cdb_s_id[TAG-1:0]));
174 
175 regfile regfile (
176     /*AUTOINST*/
177                  // Outputs
178                  .cdb_r0_id             (cdb_r0_id[TAG-1:0]),
179                  .cdb_r0_data           (cdb_r0_data[DATA-1:0]),
180                  .cdb_r1_id             (cdb_r1_id[TAG-1:0]),
181                  .cdb_r1_data           (cdb_r1_data[DATA-1:0]),
182                  .cdb_r2_id             (cdb_r2_id[TAG-1:0]),
183                  .cdb_r2_data           (cdb_r2_data[DATA-1:0]),
184                  // Inputs
185                  .clk                   (clk),
186                  .rstn                  (rstn),
187                  .cdb_a_id              (cdb_a_id[TAG-1:0]),
188                  .cdb_a_data            (cdb_a_data[DATA-1:0]),
189                  .cdb_m_id              (cdb_m_id[TAG-1:0]),
190                  .cdb_m_data            (cdb_m_data[DATA-1:0]),
191                  .cdb_l_id              (cdb_l_id[TAG-1:0]),
192                  .cdb_l_data            (cdb_l_data[DATA-1:0]),
193                  .disp_bus0             (disp_bus0[OP+4*TAG+ADDR-1:ADDR]),
194                  .disp_bus1             (disp_bus1[OP+4*TAG+ADDR-1:ADDR]),
195                  .cf_val                (cf_val),
196                  .cf_addr               (cf_addr[TAG-1:0]),
197                  .cf_data               (cf_data[DATA-1:0]));
198 
199 fadd_rs fadd_rs (
200     /*AUTOINST*/
201                  // Outputs
202                  .func_val              (fadd_val[1:0]),
203                  .func0_op              (fadd0_op[OP-1:0]),
204                  .func0_src1            (fadd0_src1[DATA-1:0]),
205                  .func0_src2            (fadd0_src2[DATA-1:0]),
206                  .func1_op              (fadd1_op[OP-1:0]),
207                  .func1_src1            (fadd1_src1[DATA-1:0]),
208                  .func1_src2            (fadd1_src2[DATA-1:0]),
209                  // Inputs
210                  .clk                   (clk),
211                  .rstn                  (rstn),
212                  .cdb_r0_id             (cdb_r0_id[TAG-1:0]),
213                  .cdb_r0_data           (cdb_r0_data[DATA-1:0]),
214                  .cdb_r1_id             (cdb_r1_id[TAG-1:0]),
215                  .cdb_r1_data           (cdb_r1_data[DATA-1:0]),
216                  .cdb_r2_id             (cdb_r2_id[TAG-1:0]),
217                  .cdb_r2_data           (cdb_r2_data[DATA-1:0]),
218                  .cdb_a_id              (cdb_a_id[TAG-1:0]),
219                  .cdb_a_data            (cdb_a_data[DATA-1:0]),
220                  .cdb_m_id              (cdb_m_id[TAG-1:0]),
221                  .cdb_m_data            (cdb_m_data[DATA-1:0]),
222                  .cdb_l_id              (cdb_l_id[TAG-1:0]),
223                  .cdb_l_data            (cdb_l_data[DATA-1:0]),
224                  .disp_bus0             (disp_bus0[OP+4*TAG+ADDR-1:ADDR]),
225                  .disp_bus1             (disp_bus1[OP+4*TAG+ADDR-1:ADDR]),
226                  .func_ack              (fadd_ack[1:0]));
227 
228 fmul_rs fmul_rs (
229     /*AUTOINST*/
230                  // Outputs
231                  .func_val              (fmul_val[1:0]),
232                  .func0_op              (fmul0_op[OP-1:0]),
233                  .func0_src1            (fmul0_src1[DATA-1:0]),
234                  .func0_src2            (fmul0_src2[DATA-1:0]),
235                  .func1_op              (fmul1_op[OP-1:0]),
236                  .func1_src1            (fmul1_src1[DATA-1:0]),
237                  .func1_src2            (fmul1_src2[DATA-1:0]),
238                  // Inputs
239                  .clk                   (clk),
240                  .rstn                  (rstn),
241                  .cdb_r0_id             (cdb_r0_id[TAG-1:0]),
242                  .cdb_r0_data           (cdb_r0_data[DATA-1:0]),
243                  .cdb_r1_id             (cdb_r1_id[TAG-1:0]),
244                  .cdb_r1_data           (cdb_r1_data[DATA-1:0]),
245                  .cdb_r2_id             (cdb_r2_id[TAG-1:0]),
246                  .cdb_r2_data           (cdb_r2_data[DATA-1:0]),
247                  .cdb_a_id              (cdb_a_id[TAG-1:0]),
248                  .cdb_a_data            (cdb_a_data[DATA-1:0]),
249                  .cdb_m_id              (cdb_m_id[TAG-1:0]),
250                  .cdb_m_data            (cdb_m_data[DATA-1:0]),
251                  .cdb_l_id              (cdb_l_id[TAG-1:0]),
252                  .cdb_l_data            (cdb_l_data[DATA-1:0]),
253                  .disp_bus0             (disp_bus0[OP+4*TAG+ADDR-1:ADDR]),
254                  .disp_bus1             (disp_bus1[OP+4*TAG+ADDR-1:ADDR]),
255                  .func_ack              (fmul_ack[1:0]));
256 
257 load_rs load_rs (
258     /*AUTOINST*/
259                  // Outputs
260                  .func_val              (load_val[1:0]),
261                  .func0_op              (load0_op[OP-1:0]),
262                  .func0_stall           (load0_stall[TAG-1:0]),
263                  .func0_address         (load0_address[ADDR-1:0]),
264                  .func1_op              (load1_op[OP-1:0]),
265                  .func1_stall           (load1_stall[TAG-1:0]),
266                  .func1_address         (load1_address[ADDR-1:0]),
267                  // Inputs
268                  .clk                   (clk),
269                  .rstn                  (rstn),
270                  .cdb_s_id              (cdb_s_id[TAG-1:0]),
271                  .disp_bus0             (disp_bus0[OP+4*TAG+ADDR-1:0]),
272                  .disp_bus1             (disp_bus1[OP+4*TAG+ADDR-1:0]),
273                  .alt_op0               (store0_op[OP-1:0]),
274                  .alt_addr0             (store0_address[ADDR-1:0]),
275                  .alt_op1               (store1_op[OP-1:0]),
276                  .alt_addr1             (store1_address[ADDR-1:0]),
277                  .func_ack              (load_ack[1:0]));
278 
279 store_rs store_rs (
280     /*AUTOINST*/
281                    // Outputs
282                    .func_val            (store_val[1:0]),
283                    .func0_pc            (store0_pc[PC-1:0]),
284                    .func0_op            (store0_op[OP-1:0]),
285                    .func0_stall         (store0_stall[TAG-1:0]),
286                    .func0_address       (store0_address[ADDR-1:0]),
287                    .func0_data          (store0_data[DATA-1:0]),
288                    .func1_pc            (store1_pc[PC-1:0]),
289                    .func1_op            (store1_op[OP-1:0]),
290                    .func1_stall         (store1_stall[TAG-1:0]),
291                    .func1_address       (store1_address[ADDR-1:0]),
292                    .func1_data          (store1_data[DATA-1:0]),
293                    // Inputs
294                    .clk                 (clk),
295                    .rstn                (rstn),
296                    .cdb_r0_id           (cdb_r0_id[TAG-1:0]),
297                    .cdb_r0_data         (cdb_r0_data[DATA-1:0]),
298                    .cdb_r1_id           (cdb_r1_id[TAG-1:0]),
299                    .cdb_r1_data         (cdb_r1_data[DATA-1:0]),
300                    .cdb_r2_id           (cdb_r2_id[TAG-1:0]),
301                    .cdb_r2_data         (cdb_r2_data[DATA-1:0]),
302                    .cdb_a_id            (cdb_a_id[TAG-1:0]),
303                    .cdb_a_data          (cdb_a_data[DATA-1:0]),
304                    .cdb_m_id            (cdb_m_id[TAG-1:0]),
305                    .cdb_m_data          (cdb_m_data[DATA-1:0]),
306                    .cdb_l_id            (cdb_l_id[TAG-1:0]),
307                    .cdb_l_data          (cdb_l_data[DATA-1:0]),
308                    .disp_bus0           (disp_bus0[OP+4*TAG+ADDR-1:0]),
309                    .disp_bus1           (disp_bus1[OP+4*TAG+ADDR-1:0]),
310                    .pc                  (rptr),
311                    .alt_op0             (load0_op[OP-1:0]),
312                    .alt_addr0           (load0_address[ADDR-1:0]),
313                    .alt_op1             (load1_op[OP-1:0]),
314                    .alt_addr1           (load1_address[ADDR-1:0]),
315                    .func_ack            (store_ack[1:0]));
316 
317 cf cf (
318     .clk                (clk),
319     .rstn               (rstn),
320     .pc                 (rptr),
321     .disp_bus0          (disp_bus0[OP+4*TAG+ADDR-1:ADDR]),
322     .disp_bus1          (disp_bus1[OP+4*TAG+ADDR-1:ADDR]),
323     .cdb_a_except       (cdb_a_except),
324     .cdb_a_id           (cdb_a_id),
325     .cdb_a_data         (cdb_a_data),
326     .cdb_m_except       (cdb_m_except),
327     .cdb_m_id           (cdb_m_id),
328     .cdb_m_data         (cdb_m_data),
329     .cdb_l_except       (cdb_l_except),
330     .cdb_l_id           (cdb_l_id),
331     .cdb_l_data         (cdb_l_data),
332     .cdb_s_except       (cdb_s_except),
333     .cdb_s_id           (cdb_s_id),
334     .exception          (exception),
335     .comp_pc            (comp_pc),
336     .clean              (clean),
337     .cf_val             (cf_val),
338     .cf_addr            (cf_addr),
339     .cf_data            (cf_data)
340 );
341 
342 
343 // Clock
344 always #2 clk <= ~clk;
345 
346 initial begin
347     $display("%t: Opening dumpfile", $time);
348     $dumpfile("dump.lxt");
349     //$dumpvars(1, tb_dispatch/fadd_rs);
350     //$dumpvars(1, tb_dispatch/fadd_pipe);
351     //$dumpvars(0, tb_dispatch/dispatch);
352     //$dumpvars(0, tb_dispatch/regstat);
353     //$dumpvars(1, tb_dispatch/regfile);
354     //$dumpvars(1, tb_dispatch/regfile/tagfileN);
355     //$dumpvars(1, tb_dispatch/regfile/regfileN);
356     //$dumpvars(1, tb_dispatch/regfile/tagfile);
357     //$dumpvars(1, tb_dispatch/regfile/regfile);
358     //$dumpvars(1, tb_dispatch/regfile/tagfile_nextN);
359     //$dumpvars(1, tb_dispatch/regfile/regfile_nextN);
360     $dumpvars(0, tb_dispatch);
361 end
362 
363 initial begin
364     clk = 1'b0;
365     rstn = 1'b0;
366 
367 
368     #10;
369     // $readmemh( "instq_stall0.hex", instq );
370     // $readmemh( "instq_ooe.hex", instq );
371     // $readmemh( "instq_all_regs.hex", instq );
372     // $readmemh( "instq_raw.hex", instq );
373     // $readmemh( "instq_war.hex", instq );
374     // $readmemh( "instq_waw.hex", instq );
375     // $readmemh( "instq_load_deps.hex", instq );
376     // $readmemh( "instq_stor_deps.hex", instq );
377     // Exceptions
378     // $readmemh( "instq_stor_dly.hex", instq );
379     // $readmemh( "instq_fsub_exp.hex", instq );
380     // $readmemh( "instq_load_exp.hex", instq );
381     // $readmemh( "instq_stor_exp.hex", instq );
382     $readmemh( "instq_double_exp.hex", instq );
383     rstn = 1'b1;
384     $readmemh( "regfile_init.hex", regfile.regfile );
385     //$readmemh( "regfile_init.hex", regfile.regfileN );
386     $readmemh( "srfile_init.hex", cf.srfile );
387     $readmemh( "srfile_init.hex", cf.srfileN );
388     #2;
389 
390     //wait (rptr == 8'd64);
391     #500;
392     $finish;
393 end
394 
395 always @( posedge clk or negedge rstn ) begin : INST_QUEUE
396     if ( !rstn ) begin
397         rptr    <= 0;
398     end
399     else begin
400         case ( inst_pop )
401         2'b00: rptr    <= rptr;
402         2'b01: rptr    <= rptr+8'd1;
403         2'b10: rptr    <= rptr+8'd1;
404         2'b11: rptr    <= rptr+8'd2;
405         endcase
406     end
407 end
408 
409 always @( posedge clk or negedge rstn ) begin : FUNC_UNITS
410     if ( !rstn ) begin
411         fadd_ack        <= 2'b00;
412         fadd_pipe[0]    <= {TAG+DATA+2{1'b0}};
413         fadd_pipe[1]    <= {TAG+DATA+2{1'b0}};
414         fadd_pipe[2]    <= {TAG+DATA+2{1'b0}};
415         cdb_a_except    <= 1'b0;
416         cdb_a_id        <= {TAG{1'b0}};
417         cdb_a_data      <= {DATA{1'b0}};
418 
419         fmul_ack        <= 2'b00;
420         fmul_pipe[0]    <= {TAG+DATA+2{1'b0}};
421         fmul_pipe[1]    <= {TAG+DATA+2{1'b0}};
422         fmul_pipe[2]    <= {TAG+DATA+2{1'b0}};
423         fmul_pipe[3]    <= {TAG+DATA+2{1'b0}};
424         fmul_pipe[4]    <= {TAG+DATA+2{1'b0}};
425         cdb_m_except    <= 1'b0;
426         cdb_m_id        <= {TAG{1'b0}};
427         cdb_m_data      <= {DATA{1'b0}};
428 
429         load_ack        <= 2'b00;
430         load_pipe       <= {TAG+DATA{1'b0}};
431         cdb_l_except    <= 1'b0;
432         cdb_l_id        <= {TAG{1'b0}};
433         cdb_l_data      <= {DATA{1'b0}};
434 
435         store_pipe      <= {TAG{1'b0}};
436         cdb_s_except    <= 1'b0;
437         cdb_s_id        <= {TAG{1'b0}};
438         cdb_s_data      <= {DATA{1'b0}};
439     end
440     else begin
441         // FADD unit
442         if (fadd_ack == 2'b11) $display ("%t: ERROR - fadd_ack = 2'b11!", $time);
443         case ( fadd_val )
444             2'b00:
445             begin
446                 fadd_ack        <= 2'b00;
447                 fadd_pipe[0]    <= {TAG+DATA+2{1'b0}};
448             end
449 
450             2'b11:
451             begin
452                 if ( fadd_ack == 2'b01 ) begin
453                     fadd_ack        <= 2'b10;
454                     fadd_pipe[0]    <= {A1, fadd1_op[0], (fadd1_src1 + fadd1_src2)};
455                     // $display( "A1, fadd1_op[0], (fadd1_src1 + fadd1_src2) = %h", {A1, fadd1_op[0], (fadd1_src1 + fadd1_src2)} );
456                 end
457                 else begin
458                     fadd_ack        <= 2'b01;
459                     fadd_pipe[0]    <= {A0, fadd0_op[0], (fadd0_src1 + fadd0_src2)};
460                     // $display( "A0, fadd0_op[0], (fadd0_src1 + fadd0_src2) = %h", {A0, fadd0_op[0], (fadd0_src1 + fadd0_src2)} );
461                 end
462             end
463 
464             2'b01:
465             begin
466                 if ( fadd_ack == 2'b01 ) begin
467                     fadd_ack        <= 2'b00;
468                     fadd_pipe[0]    <= {TAG+DATA+2{1'b0}};
469                 end
470                 else begin
471                     fadd_ack        <= 2'b01;
472                     fadd_pipe[0]    <= {A0, fadd0_op[0], (fadd0_src1 + fadd0_src2)};
473                     // $display( "A0, fadd0_op[0], (fadd0_src1 + fadd0_src2) = %h", {A0, fadd0_op[0], (fadd0_src1 + fadd0_src2)} );
474                 end
475             end
476 
477             2'b10:
478             begin
479                 if ( fadd_ack == 2'b10 ) begin
480                     fadd_ack        <= 2'b00;
481                     fadd_pipe[0]    <= {TAG+DATA+2{1'b0}};
482                 end
483                 else begin
484                     fadd_ack        <= 2'b10;
485                     fadd_pipe[0]    <= {A1, fadd1_op[0], (fadd1_src1 + fadd1_src2)};
486                     // $display( "A1, fadd1_op[0], (fadd1_src1 + fadd1_src2) = %h", {A1, fadd1_op[0], (fadd1_src1 + fadd1_src2)} );
487                 end
488             end
489         endcase
490         fadd_pipe[1]    <= fadd_pipe[0];
491         fadd_pipe[2]    <= fadd_pipe[1];
492         {cdb_a_id,
493          cdb_a_except,
494          cdb_a_data}    <= fadd_pipe[2];
495 
496         // FMUL unit
497         if (fmul_ack == 2'b11) $display ("%t: ERROR - fmul_ack = 2'b11!", $time);
498         case ( fmul_val )
499             2'b00:
500             begin
501                 fmul_ack        <= 2'b00;
502                 fmul_pipe[0]    <= {TAG+DATA{1'b0}};
503             end
504 
505             2'b11:
506             begin
507                 if ( fmul_ack == 2'b01 ) begin
508                     fmul_ack        <= 2'b10;
509                     fmul_pipe[0]    <= {M1, fmul1_op[0], (fmul1_src1 + fmul1_src2)};
510                 end
511                 else begin
512                     fmul_ack        <= 2'b01;
513                     fmul_pipe[0]    <= {M0, fmul0_op[0], (fmul0_src1 + fmul0_src2)};
514                 end
515             end
516 
517             2'b01:
518             begin
519                 if ( fmul_ack == 2'b01 ) begin
520                     fmul_ack        <= 2'b00;
521                     fmul_pipe[0]    <= {TAG+DATA{1'b0}};
522                 end
523                 else begin
524                     fmul_ack        <= 2'b01;
525                     fmul_pipe[0]    <= {M0, fmul0_op[0], (fmul0_src1 + fmul0_src2)};
526                 end
527             end
528 
529             2'b10:
530             begin
531                 if ( fmul_ack == 2'b10 ) begin
532                     fmul_ack        <= 2'b00;
533                     fmul_pipe[0]    <= {TAG+DATA{1'b0}};
534                 end
535                 else begin
536                     fmul_ack        <= 2'b10;
537                     fmul_pipe[0]    <= {M1, fmul1_op[0], (fmul1_src1 + fmul1_src2)};
538                 end
539             end
540         endcase
541         fmul_pipe[1]    <= fmul_pipe[0];
542         fmul_pipe[2]    <= fmul_pipe[1];
543         fmul_pipe[3]    <= fmul_pipe[2];
544         fmul_pipe[4]    <= fmul_pipe[3];
545         {cdb_m_id,
546          cdb_m_except,
547          cdb_m_data}    <= fmul_pipe[4];
548 
549         // LOAD unit
550         case ( load_val )
551             2'b00:
552             begin
553                 load_ack        <= 2'b00;
554                 load_pipe       <= {TAG+DATA{1'b0}};
555             end
556 
557             2'b11:
558             begin
559                 if ( load_ack == 2'b01 ) begin
560                     load_ack        <= 2'b10;
561                     load_pipe       <= {L1, load1_address[31], load1_address};
562                 end
563                 else begin
564                     load_ack        <= 2'b01;
565                     load_pipe       <= {L0, load0_address[31], load0_address};
566                 end
567             end
568 
569             2'b01:
570             begin
571                 if ( load_ack == 2'b01 ) begin
572                     load_ack        <= 2'b00;
573                     load_pipe       <= {TAG+DATA{1'b0}};
574                 end
575                 else begin
576                     load_ack        <= 2'b01;
577                     load_pipe       <= {L0, load0_address[31], load0_address};
578                 end
579             end
580 
581             2'b10:
582             begin
583                 if ( load_ack == 2'b10 ) begin
584                     load_ack        <= 2'b00;
585                     load_pipe       <= {TAG+DATA{1'b0}};
586                 end
587                 else begin
588                     load_ack        <= 2'b10;
589                     load_pipe       <= {L1, load1_address[31], load1_address};
590                 end
591             end
592         endcase
593         {cdb_l_id,
594          cdb_l_except,
595          cdb_l_data}    <= load_pipe;
596 
597         // STORE unit
598         if ( store_val[0] && comp_pc == store0_pc ) begin
599             store_pipe      <= {S0, store0_address[31], {DATA{1'b0}}};
600         end
601         else if ( store_val[1] && comp_pc == store1_pc ) begin
602             store_pipe      <= {S1, store1_address[31], {DATA{1'b0}}};
603         end
604         else begin
605             store_pipe      <= {TAG+DATA{1'b0}};
606         end
607         {cdb_s_id,
608          cdb_s_except,
609          cdb_s_data}    <= store_pipe;
610 
611     end
612 end
613 
614 assign store_ack = {( comp_pc == store1_pc ), ( comp_pc == store0_pc )};
615 
616 endmodule
617